8:15 - 8:30	Registration
8:30 - 8:35	Welcome Address by Rel/CPMT/ED Chapter Chair Mr. Wilson Tan, Micron Semiconductor Asia Pte. Ltd., Singapore
8:35 - 8:45	Opening Address by EDS Junior Past President and Founder of WIMNACT  Prof. Hiroshi Iwai, Tokyo Institute of Technology, Japan
8:45 - 9:30	High Dielectric Constant Gate Insulator Technology Prof. Hiroshi Iwai, Tokyo Institute of Technology, Japan
9:30 - 10:15	Electrical Resistance: A Bottom-up View Prof. Supriyo Datta, Purdue University, USA
10:15 - 10:45	Break
10:45 - 11:30	Carbon Nanofibers as On-chip Interconnect and Thermal Interface Materials Prof. Cary Yang, Santa Clara University, USA
11:30 - 12:15	Silicon Nanowire Devices and Their Applications to Biosensors Prof. Dim-Lee Kwong, Institute of Microelectronics, Singapore
12:15 - 1:30	Lunch
1:30 - 2:15	MOSFET Modeling Beyond 100nm Technology Prof. Mitiko Miura-Mattausch, Hiroshima University, Japan
2:15 - 3:00	Multi-Gate MOSFET Based Non-volatile Memory Design Prof. Mansun Chan, Hong Kong University of Science & Technology, Hong Kong
3:00 - 3:20	Break
3:20 - 4:05	Partnering for SoC Foundry Dr. Shih-Wei Sun, United Microelectronics Corporation, Taiwan
4:05 - 4:50	Atomic Scale Characterization for Nanoelectronic Devices Dr. Chih-Hang Tung, Institute of Microelectronics, Singapore
4:50 - 5:00	Closing remarks & presentation of tokens of appreciation

High Dielectric Constant Gate Insulator Technology
Hiroshi Iwai, Tokyo Institute of Technology, Japan

Abstract:
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference.  Now, 1.2 nm thick gate oxinitride films are used for high-speed microprocessors in production and even good operation of MOSFETS with 0.8 nm thick SiO2 gate insulator was demonstrated.  However the huge direct-tunneling leakage current through such ultra-thin gate film is a big problem and many researchers in the world have been studying and developing higher dielectric constant dielectric materials for replacing the current oxinitride film in order to suppress the gate leakage current.  In this talk, current status of the research and development for high dielectric constant gate insulator are described.

Biography:
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo and worked in the research and development of integrated circuit technology for more than 25 years in Toshiba.  He is now a professor of Frontier Collaborative Research Center and Dept. of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices.  He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors.  He has authored and coauthored more than 200 papers.

He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committees of public organizations.  For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process Integration.  He is now the Jr. Past President of the IEEE EDS, and a SRC committee member of the IEEE Technical Activity Board.  He is also a consultant professor of Huazhong University of Science and Technology, Wuhan, China, a member of DIMES Advisory Board of Delft University of Technology, the Netherlands and so on.

His awards include Local Commendation for Invention from Japan Institute of Invention and Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J. Ebers Award (2001), and JSAP Award for the best paper (2002).

His current research interests are Nano CMOS and Emerging Technologies: High–k gate insulator, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, Ge transistor, Chip Embedded and Chip Technology.

Dr. Iwai is a fellow of IEEE, a member of Electrochemical Society, a member of the Japan Society Applied Physics, a member of the Institute of Electronics, Information and Communication Engineers of Japan, and a member of the Institute of Electrical Engineers of Japan.
 

• Electrical Resistance: A Bottom-up View

Supriyo Datta, Purdue University, USA

Abstract:
It is common to differentiate between two ways of building a nanodevice: a topdown approach where we start from something big and chisel out what we want and a bottom-up approach where we start from something small like atoms or molecules and assemble what we want. When it comes to describing current flow, the standard approach could be called a “top-down” one that starts from large conductors and works its way down. In this talk I will present a “bottom-up” view of electrical conduction and use it to illustrate novel nanoscale device concepts along with fundamental questions in transport physics.

Biography:
Supriyo Datta is the Thomas Duncan Distinguished Professor in the School of Electrical and Computer Engineering, Purdue University. He received the ASEE Terman Award and shared the IEEE Cledo Brunetti Award. He is a Fellow of the IEEE, the American Physical Society (APS) and the Institute of Physics (IOP) and has authored several books including Electronic Transport in Mesoscopic Systems (Cambridge, 1995) and Quantum Transport: Atom to Transistor (Cambridge, 2005).

• Carbon Nanofibers as On-chip Interconnect and Thermal Interface Materials

Cary Yang, Santa Clara University, USA

Abstract:
As integrated circuit (IC) technology continues the trend towards sub-50 nanometer feature sizes, it is imperative to retain performance of back-end features such as on-chip interconnects while gaining the cost benefit of scaling. Some major barriers to achieving continuous downward scaling include high resistance and questionable reliability of nanoscale copper lines, and power dissipation in densely packed integrated circuits. This work presents fundamental electrical and thermal characterization of multiwall carbon nanotubes (MWNT) and carbon nanofibers (CNF) as a possible solution for next-generation back-end integrated circuit processing. Results of temperature-dependent electrical resistance measurements for MWNT and CNF arrays demonstrate distinct metallic behavior of these novel nanoscale devices. Microstructural characterization using high-resolution electron microscopy techniques are presented and its implications discussed. The use of CNF/copper composite material as a thermal interface for IC packaging is explored and fundamental thermal resistance measurement results show promise of such a composite material for thermal management applications.

Biography:
CARY Y. YANG received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Pennsylvania in 1970, 1971, and 1975, respectively.  For his doctoral research, he studied the electronic and optical properties of IV-VI narrow-gap semiconductors. His postdoctoral work at M.I.T. introduced him to the field of surface science, where he examined the detailed electronic structure of chemisorbed molecules on heavy transition metal surfaces.
He joined NASA Ames Research Center in Moffett Field, California in 1976 and extended his chemisorption study to include surfaces of submicron metal particles. Working with theoretical chemists as well as electron microscopists at Ames, he was able to model and verify the five-fold (hence non-bulk) symmetry of these particles. After a brief stay at Stanford University in the Stanford-NASA Ames Joint Institute for Surface and Microstructure Research, he founded Surface Analytic Research, Inc. in Mountain View, California, and directed sponsored research in surface and nanostructure science.  In 1983 he joined Santa Clara University and founded the Microelectronics Laboratory, for teaching and research on silicon-based devices and circuits. He currently holds the positions of Professor of Electrical Engineering, Associate Dean of Engineering, and Director of the Center for Nanostructures. At present, he is spending his sabbatical quarter as Visiting Professor at the University of California, San Diego. His current research is on nanostructure interfaces and interconnects in electronic and biological systems.
Over the past two decades, Professor Yang has initiated innovative programs to educate and train technical professionals in various stages of their careers. In the eighties, he developed and organized short courses on timely topics in silicon technology to Silicon Valley professionals. In the mid-nineties, he offered short courses on semiconductor technology for SEMI as part of a retraining program for professionals in other fields. Since the mid-eighties, he has provided opportunities for his students to spend extended periods in companies in Japan, where they collaborated with their hosts on their thesis research. More recently, he founded the Center for Nanostructures at Santa Clara, which offers interdisciplinary research and education opportunities in the field of nanoscience and nanotechnology for university students and faculty, high school students and teachers, as well as Silicon Valley technical professionals.
Dr. Yang has been a consultant to industry and government, and a visiting professor at Tokyo Institute of Technology, University of Tsukuba, National University of Singapore, University of Pennsylvania, University of California, San Diego, and University of California, Berkeley. He is a Fellow of IEEE and served as Santa Clara Valley Chapter Chair, Regions/Chapters Chair, Vice President, and President of the IEEE Electron Devices Society.  In 2001, on behalf of People to People Ambassadors Program, he led an Electron Devices Delegation to visit universities, government institutes, and companies in the People’s Republic of China. From 2002 to 2003, he served as an elected member of the IEEE Board of Directors, representing Division I.  He was an editor of the IEEE Transactions on Electron Devices, in the area of MOS devices. In 2004, he was named the recipient of the IEEE Educational Activities Board Meritorious Achievement Award in Continuing Education "for extensive and innovative contributions to the continuing education of working professionals in the field of micro/nanoelectronics". In 2005, he was honored with the IEEE Electron Devices Society Distinguished Service Award.

• Silicon Nanowire Devices and Their Applications to Biosensors

Dim-Lee Kwong, Institute of Microelectronics, Singapore

Abstract:
In the last decade, there has been tremendous advancement in the development of novel nanotechnology for future electronics, such as for high-performance, low-power logic IC. The challenges and opportunities have been widely discussed by many major semiconductor manufacturers, who have been focusing on the choices of materials, processes of implementation (e.g., high-k, metal-gate, high-carrier mobility substrates, strain-engineering, etc) and innovative non-planar device structures. For instances, the issues of mobility degradation, Vt-control, high source/drain resistance in 3D device structures are few examples that trigger huge interest among IC research and development communities. How to form 3D device structure based on standard Si-manufacturing tool sets presents extra layer of challenge.

With the confidence that industry will always be creative enough to overcome these obstacles to stay in line with the Moore’s law, it is desirable for these technologies to identify their uniqueness, and find a wider scope of applications. Si nanowire based device structure is one such candidate. On one hand, it is a perfect MOSFET device with all-around-gated body, which possesses excellent electrostatic control and scalability, for logic electronics. On the other hand, it can also be used as a highly sensitive bio-detecting element because of their high surface to volume ratio.

At IME, we fabricate Si nanowires using CMOS based process technologies. Gate All Around MOSFETs with excellent electrostatic control and high drive current have been achieved for single wires, 3D stacked nanowires and SiGe nanowires.

As a newer application, we are now investigating the bio-molecule detection using arrays of Si nanowires. These arrays are integrated with microfluidics for effective sample delivery. Bio-molecule detection requires the development of various bio-chemistry protocols coupled with the suitable electrical test conditions for different target applications. Examples of a simple sensing mechanism wherein the nanowire conduction changes in response to ionic solutions and bio-molecule attachment on functionalized surfaces will also be presented along with strategies to enhance sensitivity.

Biography:
Dim-Lee Kwong is the Executive Director of Institute of Microelectronics (IME), Singapore, Professor of Electrical and Computer Engineering and holds the Earl N. and Margaret Brasfield Endowed Professorship at the University of Texas at Austin. Prof. Kwong is the author of more than 350 referred archival journal and 310 referred archival conference proceedings publications, has presented more than 50 invited talks at international conferences, and has been awarded with more than 25 U.S. patents. His current areas of research interests include novel materials and structures for Si-based nano devices, nano-scale nonvolatile memory devices, advanced RF and opto-electronic micro-systems, Si-based biosensors and lab-on-chip. 48 students received their Ph.D. degrees under his supervision. Professor Kwong was the founder of Rapro Technology in 1986, Micro Integration Corporation in 1988 and ASECTO in 2001. He has been consultant to semiconductor IC manufacturers, suppliers, and equipment companies in US and overseas.

• MOSFET Modeling Beyond 100nm Technology

Mitiko Miura-Mattausch, Hiroshima University, Japan

Abstract:
Evolution of compact models is reviewed. The development trend leads to models based on the channel surface potential, allowing higher accuracy and reduced number of model parameters. It is demonstrated that the model accuracy for higher-order phenomena, which is prerequisite for accurate RF circuit simulation, can be achieved without any new model parameters in addition to those for describing the I V characteristics.

Biography:
Mitiko Miura-Mattausch is a professor in Department of Semiconductor Electronics and Integration Science, Graduate School of Advanced Sciences of Matter at Hiroshima University. Before becoming a professor, she joined the Max-Planck-Institute for solid-state physics in Stuttgart, Germany as a researcher working with non-linear phenomena in solid state (1981-1984), and was with Corporate Research and Development, Siemens AG, Munich, Germany, working on hot-electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of deep submicron MOSFETs for circuit simulation (1984-1996). Since 1996 she is leading the ultra-scaled devices laboratory and focusing on advanced MOSFETs feature under RF operation experimentally and theoretically. She has supervised 5 PhD works and is still growing. She has published more than 160 publications and a coauthor of three technical books. Prof. Miura-Mattausch serves as a committee member of several international conferences, and a member of IEEE Compact Modeling Technical Committee.

• Multi-Gate MOSFET Based Non-volatile Memory Design

Mansun Chan, Department of Electrical and Electronic Engineering, Hong Kong University of Science & Technology, Hong Kong

Abstract:
Scaling of non-volatile Memory such as FLASH EEPROM has been lack behind of conventional CMOS technology due to the difficulty to scale the tunneling oxide that leads to more serious short channel effects.  The scaling of CMOS technology in the sub-50nm regime requires the use of non-conventional structure such as ultra-thin body or multi-gate MOSFETs.  In this work, we have studied some potential approach to utilize the knowledge obtained from multi-gate MOSFETs to design non-volatile memory.  The introduction of more than one conductive surfaces allow the programmed charge to be stored at multiple locations.  The programming and erase mechanism, however, require careful design to avoid disturbs and reliability issues.

Biography:
Mansun Chan received his BS degree in Electrical Engineering (highest honors) and BS degree in Computer Sciences (highest honors) in 1990 and 1991 respectively, both from University of California at San Diego. He completed his MS degree in 1994 and Ph.D degree in 1995 at University of California at Berkeley. During his undergraduate study, he has been working with Rockwell International Laboratory on Heterojunction Bipolar Transistor (HBT) modeling, where he developed the self-heating SPICE model for HBT. His research at Berkeley covered a broad area in silicon devices ranging from process development to device design, characterization, and modeling. A major part of his work was on the development of record breaking Silicon-On-Insulator (SOI) technologies. Dr. Chan has also maintained a strong interest in device modeling and circuit simulation. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology. His research interests include nano-device technologies, image sensors, SOI technologies, high performance IC, 3D Circuit Technology, device modeling and Nano BIOMEMS technology. Between July 2001 and December 2002, he was a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program. He is currently still consulting on the development of the next generation BSIM model.

Dr. Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award (1999) and the Distinguished Teaching award (2004). He is a Senior Member and Distinguished Lecturer of IEEE.

• Partnering for SoC Foundry

Shih-Wei Sun, United Microelectronics Corporation, Taiwan

Abstract:
The proliferation of System on Chip (SoC) designs have created a whole new market of smart products that have decreased in size while greatly increasing in functionality.  However, new challenges have made it more difficult for designers to achieve first-time-right silicon success in time to meet market windows.  For designers to be successful, a comprehensive SoC solution package that covers the entire chip development is needed.

UMC collaborates closely with customers as well as partners throughout the entire supply chain, including equipment, EDA tool, and IP vendors to work synergistically towards each customer's SoC silicon success.  This has resulted in a broad range of resources available to SoC designers, including silicon validated reference flows, a broad IP portfolio, libraries, and cost effective prototyping.  We also understand system implications so that we can engage in robust dialogue and offer suggestions for optimizing system partition for each design.

Combining these with our advanced 90nm, 65nm and below process technologies, extensive package and test capabilities, and state-of-the-art 300mm manufacturing, the result is complete SoC foundry solution to deliver successful results in a timely fashion.

Biography:
Shih-Wei Sun currently serves as UMC’s Senior Vice President in charge of Central Research and Development. Dr. Sun joined UMC in 1995 to lead the 0.25um advanced technology development efforts. He was also responsible for the operation of UMC’s 6A, 8AB, and 8D fabs. Prior to joining UMC, Dr. Sun worked for Motorola in the Advanced Products Research and Development Laboratory (APRDL) for 10 years. He received his Ph.D. degree in Materials Science and Engineering from Northwestern University in 1985. Shih-Wei was the recipient of the Outstanding Electrical Engineer Award from the Chinese Institute of Electrical Engineering in 1998, the Chinese Management Excellence Award in 2000, and the 10th National Invention Award in 2001.  He also served as the Committee Member, Chair, and Asia Arrangement Co-Chair of International Electron Device Meeting (IEDM) from 1995 to 2000.

• Atomic Scale Characterization for Nanoelectronic Devices

Chih-Hang Tung, Institute of Microelectronics, Singapore

Abstract:
The need for powerful analytical tool in semiconductor R&D and production environment has never been stronger as traditional CMOS device critical dimension shrinks below 65 nm. Diversification in device varieties & manufacturing technologies and integration among them has pushed our fundamental knowledge of materials and interfaces to the atomic level. Transmission electron microscopy provides the ultimate atomic resolution needed. Two key analytical capabilities, local lattice strain and chemical bonding are discussed and demonstrated with examples to show how TEM can provide the needed information at the atomic level for R&D and productions of nanoelectronic devices.

Biography:
Chih Hang Tung has been working in semiconductor R&D and production for more than 18 years. He had worked in ERSO/ITRI and Vanguard International Semiconductor Corp in Taiwan before he joined Institute of Microelectronics in Singapore. His main research interests are in semiconductor process technology development and characterization techniques. He has more than 130 publications in prestigious journals and conferences and authored a book (ULSI Semiconductor Technology Atlas, John Wiley, 2003). Chih Hang is an IEEE EDS Distinguished Lecturer and an IEEE senior member. He is the Technical Chair of IPFA 2006, Technical Co-chair IPFA 2005 and joined in IPFA organization committee since 2001. He is a Guest Editor of IEEE T-DMR and a regular reviewer of IEEE TED and EDL.

Report on the 11th WIMNACT-Singapore
(By Xing Zhou, Wilson Tan, and Kin-Leong Pey)

The 11th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-Singapore) was successfully held on July 4, 2006 at Meritus Mandarin Hotel in Singapore.  This mini-colloquium is the 4th one organized and sponsored by the IEEE Rel/CPMT/ED Singapore Chapter, with co-sponsorship from the EDS Distinguished Lecturer (DL) Program.  The event was held together with the 13th International Symposium on the Physical & Failure Analysis of Integrated Circuits (IPFA’2006), in celebration of the 20th anniversary of IPFA.  After the welcome address by the Chapter Chair, Mr. Wilson Tan, Prof. Hiroshi Iwai, EDS Jr. Past President and founder of WIMNACT series, delivered an opening address with a brief history of all the past-year WIMNACT’s.

There were eight invited speakers, including six DL from overseas.  The Workshop started with the talk given by Prof. Hiroshi Iwai from Tokyo Institute of Technology entitled “High Dielectric Constant Gate Insulator Technology,” followed by the talk on “Electrical Resistance: A Bottom-up View” given by Prof. Supriyo Datta from Purdue University.  Prof. Cary Yang from Santa Clara University gave the talk on “Carbon Nanofibers as On-chip Interconnect and Thermal Interface Materials.”  The morning session concluded with the talk on “Silicon Nanowire Devices and Their Applications to Biosensors” by Dr. N. Balasubramanian from the Institute of Microelectronics (IME, Singapore).  The afternoon session had four DL talks: “MOSFET Modeling Beyond 100nm Technology” by Prof. Mitiko Miura-Mattausch from Hiroshima University, “Multi-Gate MOSFET Based Non-volatile Memory Design” by Prof. Mansun Chan from Hong Kong University of Science & Technology, “Partnering for SoC Foundry” by Dr. Shih-Wei Sun from UMC, and “Atomic Scale Characterization for Nanoelectronic Devices” by Mr. Chih-Hang Tung of the IME, Singapore.  The Workshop ended with a concluding remark by the Chapter Secretary, Prof. Kin-Leong Pey, and presentation of tokens of appreciation to all the speakers by the Chapter Chair, Mr. Wilson Tan.

The Workshop was attended by more than 80 participants from the local industries and academic institutions.  A membership drive was also held in conjunction with the WIMNACT and IPFA, with many new IEEE members signed up.  The 11th WIMNACT-Singapore has been another successful event, which the Singapore Chapter has contributed towards the EDS and its members.  The complete information on the 11th WIMNACT-Singapore, including the slides and snapshots as well as links to the past WIMNACT series, has been made available from the following website:

http://www.ntu.edu.sg/eee/eee6/conf/WIMNACT06.htm

 

	Hiroshi Iwai, High Dielectric Constant Gate Insulator Technology
	Supriyo Datta, Electrical Resistance: A Bottom-up View
	Cary Yang, Carbon Nanofibers as On-chip Interconnect and Thermal Interface Materials
	Mitiko Miura-Mattausch, MOSFET Modeling Beyond 100nm Technology
	Mansun Chan, Multi-Gate MOSFET Based Non-volatile Memory Design
	Shih-Wei Sun, Partnering for SoC Foundry
	Chih-Hang Tung, Atomic Scale Characterization for Nanoelectronic Devices

Click to view snapshots from the Workshop.

Rel/CPMT/ED Singapore Chapter	http://ewh.ieee.org/soc/cpmt/singapore
1st  WIMNACT-China	http://www.ieee.org/organizations/pubs/newsletters/eds/apr03/china.html
2nd WIMNACT-Korea	http://www.ieee.org/organizations/pubs/newsletters/eds/jan04/2nd_wimnact.html
3rd WIMNACT-Singapore	http://www.ntu.edu.sg/eee/eee6/conf/WIMNACT.htm (EDS Newsletter)
4th WIMNACT-Singapore	http://www.ntu.edu.sg/eee/eee6/conf/WIMNACT04.htm (EDS Newsletter)
5th WIMNACT-Hong Kong	http://www.ee.ust.hk/ieee_eds/wimnact04/wimnact04.htm (EDS Newsletter)
6th WIMNACT-Taiwan	Jan. 21-22, 2005, National Chiao Tung University, Taiwan (EDS Newsletter)
7th WIMNACT-Korea	June 3, 2005, Hanyang University, South Korea (EDS Newsletter)
8th WIMNACT-Singapore	http://www.ntu.edu.sg/eee/eee6/conf/WIMNACT05.htm (EDS Newsletter )
9th WIMNACT-Janpan	Oct. 25, 2005, Tokyo Institute of Technology, Japan (EDS Newsletter)
10th WIMNACT-China	Mar. 13-27, 2006, Chengdu, Wuhan, Harbin, China (EDS Newsletter)
11th WIMNACT-Singapore	http://www.ntu.edu.sg/eee/eee6/conf/WIMNACT06.htm
IPFA 2006	http://ewh.ieee.org/reg/10/ipfa/html/2006/indexm.htm  (advance programme )
IEEE Membership Online Application	http://services1.ieee.org/membersvc/member/mem_intro.htm