Dear invited guests and distinguished speakers, ED Singapore Chapter chair and committee members, fellow colleagues, ladies and gentlemen,

Welcome to WIMNACT-Singapore -- the third Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology!  I would first like to congratulate the IEEE Electron Devices Singapore Chapter for organizing this one-day event, and thanks to the efforts of its committee members and the financial support from the Chapter as well as the EDS Asia-Pacific Subcommittee of Regions/Chapters and the EDS Headquarter.  I would also like to thank our invited Distinguished Lecturers and speakers, both overseas and local, for their participation in the Workshop, which makes this event truly international and outstanding.

It is our honor to have the third WIMNACT being held in Singapore and associated with NTU and Microelectronics Division.  The IEEE Electron Devices Society’s Distinguished Lecturer Program and its mini-colloquium series have been well known in delivering outstanding lectures, workshops, and educational programs on topics of the state-of-the-art technologies.  The first WIMNACT series was initiated in November 2002, with a 9-day program in 4 cities in China: Shanghai, Nanjing, Xi’an, and Beijing.  The second WIMNACT has just been held in Korea on 19 September.  For this third WIMNACT, we are happy to have distinguished lecturers from Taiwan National Chiao Tung, Hong Kong UST, and Japan Hiroshima University, as well as researchers from NUS and NTU, who are eminent experts in their respective fields.  The topics of the Workshop cover advanced issues in CMOS technology development in the morning session, which include low-voltage/low-power and high-speed flash memory technology, electrostatic discharge in submicron devices, and ultrashallow junction formation for sub-100nm technologies; and new device structures and modeling in the afternoon session, which include circuit models for coming MOSFET generations, nano-CMOS technology options, and the link to seamless simulation.  As the mainstream CMOS technology advancements continue on the famous Moore’s Law into the nanometer regime, new issues and challenges arise in both technology development and modeling, as well as new opportunities and options in non-conventional MOS technologies.  This Workshop will provide a glimpse of some important issues to be addressed in the current and future technology nodes.  With the enthusiastic response as seen from more than a hundred pre-registrations before the Workshop, I am sure the audience will find this Workshop to be interesting and beneficial.

The sponsorship of IEEE and participation of international eminent experts in WIMNACT is also very timely as Singapore and Asia-Pacific region is embarking on joining the global semiconductor roadmap of advanced technologies.  This is witnessed by more than 80 pre-registrations received from local industries and neighboring countries.  We are also very glad to have this opportunity to demonstrate our existing and new programs in the area of nano-CMOS in the Microelectronics Division, which will be briefed by our Program Directors for the Silicon Technology and Computational Nano-Electronics research groups.  We have also planned a session for interested staff to interact with the invited speakers, and a lab tour for our invited guests at the end of the Workshop.

On behalf of the Microelectronics Division and the School of EEE, it is my great pleasure to extend a warm welcome to everyone attending this Workshop, and I wish all of you a pleasant day in NTU for a successful Workshop.  Thank you!

• Low Voltage/Power and High Speed Flash Memory Technology for High Performance and Reliability

Steve S. Chung, Department of Electronic Engineering, National Chiao Tung University, Taiwan

Abstract:
The floating gate flash memory has been one of the most successful nonvolatile memory in the past two decade. However, it requires high gate voltage for programming and erase which limit the device scaling and reliability. In this talk, we will address different strategies for designing floating gate flash memories with high performance and high reliability, for achieving low power and high speed performance. Various schemes and cell structures will be introduced to meet the low voltage, low power, and high speed requirements. Also, the possibility for a further scaling of flash memory cells based on different gate oxide engineering will be presented.

Biography:
Steve S. Chung received his Ph.D. degree from the University of Illinois at Urbana-Champaign, in Electrical Engineering. Currently, he is a Professor with the Electronic Engineering Department at the National Chiao Tung University, Taiwan. He has over 24-year teaching experience in the university. He has also been a consultant to major semiconductor companies in Hsinchu Science-Based Industrial Park, Taiwan. During the Fall Quarter of 2001, he has been a Research Visiting Scholar with Stanford University, CA. His current teaching and research interests are in the areas of advanced CMOS device technology; characterization and reliability study of CMOS/flash memory devices and circuits; modeling and simulation of MOS devices/SOI/non-volatile memories and TFTs; and TCAD. He has published more than 130 journal articles and conference papers in these areas. He is also the author of one undergraduate textbook. He holds more than 14 US and ROC patents.
Dr. Chung has ever served as a committee member in various IEEE conferences, including VLSI Technology Symposium, IEDM, IRPS, ICMTS, ASIC, VLSI-TSA etc.  Since June 2000, he has been the Chair of EDS Taipei Chapter, which was awarded 2002 IEEE EDS Chapter of the Year Award. Currently, he is also a DL (Distinguished Lecturer) of EDS, an Editor of EDL. He also served as Award Committee Chair of the EDMA (Electron Devices and Materials Association), Taiwan. He has received three times the Excellent Research Award, and 1996-1998, 2000-2002 Outstanding Research Award, from the National Science Council, Taiwan. In 2001, he was granted a Distinguished Engineering Professor Award by the Chinese Institute of Electrical Engineering (CIEE), Taiwan.
He is a Senior member of IEEE, member of EDMA and CIEE, and was listed in Marquis Who’s who in the world, 1999-2001 and Who’s who in finance, 2000.

• ESD in Sub-Micron Devices: Issues and Challenges

M. K. Radhakrishnan, Device Reliability Consultant and Adjunct Faculty, National University of Singapore, Singapore

Abstract:
With rapid growth of technology in deep-submicron regime and CMOS RF devices operating above many giga-hertz in countless applications and segments of life, the ESD reliability of these devices are emerging as one of the major bottlenecks which is not yet effectively tackled. In this talk, the challenges faced from both the circuit design point of view, as well as technology generations will be reviewed. Significant points related to 0.25um-100nm CMOS technologies will be discussed which will contain published data on various case studies. Guidelines and methods to integrate ESD design for RF circuits will be discussed. This talk will also provide an introduction to ESD reliability in general through reviewing the issues in various technologies, such as Silicon, Silicon Germanium, BiCMOS, SOI, etc along with ESD/RF characterization methodologies. Further, the influence of the process and scaling will be discussed and a brief overview of the ESD induced failures in devices related to different technologies will be presented with appropriate case studies.

Biography:
Dr. M. K. Radhakrishnan received Ph.D for Semiconductor Thin Film studies in 1981 from CUSAT, India and has more than 25 years experience in the semiconductor device manufacturing, device analysis and quality and reliability studies, at various institutions including avionics research, semiconductor manufacturing and independent R&D laboratories. He is a Consultant in the area of Device Reliability and has worked with a number of wafer fabs and packaging industry in Asia and Europe as well as with many organizations including International Telecom Union (ITU), Geneva. He was the General Chairman for IEEE IPFA’99 and is TPC member of many international conferences like IRPS, ESREF and EOS/ESD symposium.  Dr. Radhakrishnan is the Editorial Board Member of Microelectronics Reliability journal (UK) and Journal of Semiconductor Technology and Science (JSTS). He is an adjunct faculty in the National University of Singapore. He is an IEEE EDS Distinguished Lecturer and has designed and conducted a number of invited tutorials, workshops and courses at various international conferences on various aspects of IC Device Analysis & Reliability. He has more than 50 research publications in the field. He is a Senior Member of IEEE, Member of ESD Association, USA and Member of EDFAS, USA.

• Ultrashallow Junction Formation for Sub-100nm Technologies Using Pulsed Excimer Laser

Kin Leong Pey, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore

Abstract:
In the fabrication of ultra-large scale integrated circuits, one crucial step is to shrink the critical dimension of the polycrystalline silicon gate. As a result, short channel effects (SCE) become more prominent and thus ultra-shallow junctions are needed to prevent SCE. After ion implantation to dope the source/drain extensions, the wafers are normally subjected to a high-temperature anneal to activate the dopants. Due to the transient enhanced diffusion (TED) of boron, there is a lot of concerns on the thermal budget of the post-implantation anneal. Ultra-shallow junctions can be obtained by using ultra-low energy ion implantation followed by spike rapid thermal annealing (RTA). An extreme case of RTA is laser thermal processing (LTP), which involves the laser irradiation of the silicon substrate with ramp-up rates so high that it can melt the surface regions, without melting the bulk.
The results of ultra-shallow p+/n junctions fabricated using pre-amorphization of silicon to enhance melting of silicon during LTP will be presented. Comparison will be made to spike annealed junctions.  Recent results of using non-melt approach will be shown. The effects of the substrate type such as bulk silicon and silicon on insulator on LTP will be discussed.

Biography:
Kin-Leong Pey received the Bachelor of Engineering (1989) and the Ph.D (1994) in Electrical Engineering from the National University of Singapore. He has held various research positions in the Institute of Microelectronics, Chartered Semiconductor Manufacturing, and National University of Singapore. KL Pey is currently an Associate Professor in the School of Electrical & Electronics Engineering, Nanyang Technological University, Singapore and a Fellow in the Singapore-MIT Alliance (SMA). He is a senior member of IEEE and was the organizing committee member of IPFA95, 97, 99, 2002, 2003 and the General Chair of IPFA2001. He has published more than 120 technical papers, including 2 recent papers in IEDM, and holds 25 US patents.

• Circuit Simulation Models for Coming MOSFET Generations

Mitiko Miura-Mattausch, Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan

Abstract:
Requirements for circuit simulation are increasing due to two ongoing developements, namely, the down scaling of MOSFETs into the sub-100nm regime and system integration with many different functions on a single chip. To assist in the development, the most important modeling issue is to guarantee sufficient simulation accuracy and applicability for any advanced technology. Here we discuss different modeling approaches, with emphasis on surface-potential-based models, to realize the requirements.

Biography:
Mitiko Miura-Mattausch received the Dr. Sc. Degree from Hiroshima Univerisity. She joined the Max-Planck-Institute for solid-state physics in Stuttgart, Germany as a researcher from 1981 to 1984. From 1984 to 1996, she was with Corporate Research and Development, Siemens AG, Munich, Germany, working on hot-electron problems in MOSFETs, the development of bipolar transistors, and analytical modeling of deep submicron MOSFETs for circuit simulation.  Since 1996, she has been a professor in Department of Electrical Engineering, Graduate School of Advanced Sciences of Matter at Hiroshima University, leading the ultra-scaled devices laboratory.

• Nano-CMOS Technology Options: From Traditional to Futuristic Device Structures

Mansun Chan, Department of Electrical and Electronic Engineering, Hong Kong University of Science & Technology, Hong Kong

Abstract:
In this presentation, the requirements for nano-CMOS devices will be reviewed.  Various technology options including high-k dielectrics, metal gates electrode, source/drain engineering, strained silicon, and Schottky source/drain will be examined.  While these technology options provide potential solutions to the scaling crisis of traditional CMOS technology, their utilization remains challenging and results in new issues.  The migration to non-traditional device structure such as double-gate MOSFETs, multi-gate quantum wire FET and single electron transistor has been actively pursued.  New challenges and opportunities in the application of these new devices will be discussed.

Biography:
Dr. Mansun Chan received his BS degree in Electrical Engineering (highest honors) and BS degree in Computer Sciences (highest honors) in 1990 and 1991 respectively, both from University of California at San Diego. He completed his MS degree in 1994 and Ph.D degree in 1995 at University of California at Berkeley. During his undergraduate study, he has been working with Rockwell International Laboratory on Heterojunction Bipolar Transistor (HBT) modeling, where he developed the self-heating SPICE model for HBT. His research at Berkeley covered a broad area in silicon devices ranging from process development to device design, characterization, and modeling. A major part of his work was on the development of record breaking Silicon-On-Insulator (SOI) technologies. Dr. Chan has also maintained a strong interest in device modeling and circuit simulation. He is one of the major contributors to the unified BSIM model for SPICE, which has been accepted by most US companies and the Compact Model Council (CMC) as the first industrial standard MOSFET model. In January 1996, he has joined the EEE faculty at Hong Kong University of Science and Technology. His research interests include nano-device technologies, image sensors, SOI technologies, high performance IC, 3D Circuit Technology, device modeling and Nano BIOMEMS technology. Starting from July 2001, he is a Visiting Professor at University of California at Berkeley and the Co-director of the BSIM program.
Dr. Chan is a recipient of the UC Regents Fellowship, Golden Keys Scholarship for Academic Excellence, SRC Inventor Recognition Award, Rockwell Research Fellowship, R&D 100 award (for the BSIM3v3 project), Teaching Excellence Appreciation award (1999) and other awards. He is a Senior Member and a Distinguished Lecturer of IEEE.

• The Missing Link to Seamless Simulation

Xing Zhou, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore

Abstract:
The trends and needs in multi-level modeling of ULSI systems are reviewed in the context of nanometer CMOS technology, with an emphasis from the model/tool developer’s perspective.  A dual representation of transistors/circuits is proposed and demonstrated through physics-based transistor compact modeling and a single-engine circuit simulator.  Extension to process correlation and block-level representation is also proposed, which will be the key to studying process effects on system performance.  This consistent dual representation allows detailed physics captured at a lower level to be propagated to the higher level of abstraction.  The key idea is to build a physics-based device compact model (CM) based on technology characterization, which serves as the building block for an implicit multi-level circuit simulator based on a subcircuit-expansion approach.  In this way, process variation can be captured through device CMs, and its effects on circuit/system performance can be linked to a consistent hierarchy of abstractions within the same simulator engine.

Biography:
Xing Zhou obtained his BEng degree in electrical engineering from Tsinghua University in 1983, MS and PhD degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively.  He is currently an Associate Professor in the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, where he engaged in teaching and research activities.  He is Program Director for the Computational Nano-Electronics Group in the School.  His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development.  His recent research focuses on nanoscale CMOS technology and device compact modeling.  He was a Visiting Fellow at the Center for Integrated Systems, Stanford University during 1997 and 2001, and a Visiting Professor at Hiroshima University in January 2003.  He is the organizer for the Workshop on Compact Modeling in collaboration with the International Conference on Modeling and Simulation of Microsystems in Puerto Rico (2002), San Francisco (2003), and Boston (2004).  He has published widely in international journals and has been invited to give talks in a number of international conferences and numerous companies, universities, and research institutes.
Dr. Zhou is a senior member of the IEEE, a member of the IEEE EDS VLSI Technology and Circuits as well as Compact Modeling technical committees, a member of the EDS Regions/Chapters Committee, and an EDS Distinguished Lecturer.

The 3rd Workshop and IEEE EDS Mini-colloquia on NAnometer CMOS Technology (WIMNACT-Singapore) was held on Oct. 15, 2003 in Singapore, organized and sponsored by the IEEE Rel/CPMT/ED Singapore Chapter, and sponsored by the EDS Asia-Pacific Subcommittee of Regions/Chapters and the EDS Headquarter.  Microelectronics Division of the School of Electrical & Electronic Engineering (EEE) at Nanyang Technological University (NTU) hosted this one-day event, composed of 3 DL’s from Taiwan, Japan, and Hong Kong sent by the EDS and 2 local DL’s and one Chapter committee member.  After the welcome address by the Guest-of-Honor and Head of Microelectronics Division, Dr. Ooi Kiang Tan, Chapter Vice Chair, Y. C. Ng, delivered an opening address on behalf of Chapter Chair, Dr. Soon Huat Ong, in which he also reviewed Chapter activities in the past years.  This was followed by brief introductions of the Silicon Technology and Computational Nano-Electronics groups in the Microelectronics Division by the respective Program Directors, Dr. Kin Leong Pey and Dr. Xing Zhou.

The first talk was given by Dr. Steve Chung from National Chiao Tung University entitled “Low Voltage/Power and High Speed Flash Memory Technology for High Performance and Reliability,” followed by the talk on “ESD in Sub-micron Devices: Issues and Challenges” given by Dr. M. K. Radhakrishnan.  The morning session ended with the talk by Dr. Kin Leong Pey on “Ultrashallow Junction Formation for Sub-100nm Technologies Using Pulsed Excimer Laser.”  After lunch at the NTU staff club with the invited guests and Chapter committee members, Dr. Mitiko Miura-Mattausch from Hiroshima University gave the talk on “Circuit Simulation Models for Coming MOSFET Generations,” following by the talk on “Nano-CMOS Technology Options: From Traditional to Futuristic Device Structures” given by Dr. Mansun Chan of Hong Kong University of Science & Technology.  The Workshop ended with the talk by Dr. Xing Zhou on “The Missing Link to Seamless Simulation.”  All the speakers were presented with a token of appreciation by the Chapter.  After an interactive session with the speakers, the invited guests were given a tour of the MicroFabrication Lab (MFL) in the School of EEE, an SGD$25m 6” CMOS teaching/research facility, briefed by the Program Manager, Prof Man Siu Tse.  The full-day event was ended with the dinner for the invited DLs hosted by the Chapter.

In summary, the 3rd WIMNACT-Singapore was a very successful event.  The Workshop received enthusiastic response with ~130 pre-registrations and more than 110 attendees, more than half of them were from the local industries, with participants from neighboring countries as well, and most of them stayed for the entire full-day event.  They showed deep interests in the invited talks and many followed up on enquires for the speakers’ presentation slides.  The complete information on the 3rd WIMNACT-Singapore, including all the slides and snapshots, has been made available from the following website:

 

Steve S. Chung, Low Voltage/Power and High Speed Flash Memory Technology for High Performance and Reliability

Kin Leong Pey, Ultrashallow Junction Formation for Sub-100nm Technologies Using Pulsed Excimer Laser

Mitiko Miura-Mattausch, Circuit Simulation Models for Coming MOSFET Generations

Mansun Chan, Nano-CMOS Technology Options: From Traditional to Futuristic Device Structures

Xing Zhou, The Missing Link to Seamless Simulation

Rel/CPMT/ED Singapore Chapter	http://ewh.ieee.org/soc/cpmt/singapore
Silicon Technology Group	http://www.ntu.edu.sg/eee/eee6/SiTech/
Computational Nano-Electronics Group	http://www.ntu.edu.sg/eee/eee6/CNEI/
1st  WIMNACT-China	http://www.ieee.org/organizations/pubs/newsletters/eds/apr03/china.html
2nd WIMNACT-Korea	http://www.ieee.org/organizations/pubs/newsletters/eds/jan04/2nd_wimnact.html
3rd WIMNACT-Singapore	Program / Abstracts  / Report / EDS Newsletter
Workshop on Compact Modeling	http://www.ntu.edu.sg/home/exzhou/WCM/ (WCM-MSM2004)
IPFA 2004	http://ewh.ieee.org/reg/10/ipfa/
ThinFilms 2004 & NanoTech 2004	http://www.nanotech2004.org/