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 Low-dimensional
physics and chemistry
Staff: Dr Ang Lay Kee, Ricky (coordinator), Dr Au Yeung Tin Cheung, Dr Sun Chang Qing Nano-technology
and nano-devices
Staff: Dr Chen Tupei (coordinator), Dr Pey Kin Leong, Dr Rusli, Dr Zhou Xing
Description: My research concentrates on the theoretical analysis and simulation of interaction of intense beam with its surrounding (vacuum or collisionless) nanostructures. Since 2000, we have started developing using quantum theory to exploit the beam-structure interaction in nanometer regime, where the classical theory fails. This research is focused on developing a quantum circuit model to describe all the classical concepts that were use in vacuum electronics, such as limiting current, detune and de-Q of a cavity by the presence of electron beam, noise figure, etc. It seems natural since various kinds of nanostructures (i.e., gaps, cavities, wires, and tubes) envisioned all have their counterparts in conventional vacuum electronics. It should be emphasized array of vacuum nanodiodes and nanotriodes with a small dimension (30 nm) can emit mean high current density (>100 A/cm2) or local high current density (> 107 A/cm2) is feasible. This research is supported with a start-up grant from NTU and is collaborated with researchers in Los Alamos Nat Lab and U Michigan in United States. In my group, we are also interested in using MAGIC3D (by Mission Research Corp) and OOPIC (by UC Berkeley) to simulate a wide range of beam and plasma related problems, which includes a. Simulation of various field emitter array b. Plasma-induced quantum-well intermixing c. ICP-CVD for nano-size thin film deposition These activities are in parallel with experimental works conducted in various research groups in microelectronic center in NTU, including Diamond, Photonics, and Sensors. The funding for these projects are mainly from NTU (AcRF) and A*STAR (Singapore government). Quantum/spin
transport in quantum-dot systems
Contact: Dr Au Yeung Tin Cheung Description: (1) Quantum Transport in Quantum Dot Systems in the Presence of Coulomb Interaction Between Various Capacitances: The problem of Coulomb blockade and Resonant Tunneling in tunneling-coupled quantum dot systems has been investigated throughout in the past few years. The previous works did not take into account the coulomb interaction between various capacitances such as the tunneling, inter-dot and gate capacitances. Dr Au Yeung is now working on the effect of the coulomb interaction between various capacitances on the Coulomb Blockade and Resonant Tunneling. His investigation consists of three steps: (a) To establish a transport model which is gauge invariant in the presence of coulomb interaction; (b) To derive a general expression for the tunneling current that can apply under various conditions such as high field and high frequency; (c) To analysis in details the effect of coulomb interaction between various capacitances on the Coulomb Blockade and Resonant Tunneling phenomena. (2) Spin Transport in Tunneling-Coupled Quantum Dot Systems: The transport of electrons carrying spin in quantum dot systems has important application to memory devices. For this application, it is crucial to control the distribution of electrons in every dots during the electronic transport process. Dr Au Yeung investigations involve three steps: (a) To find out the spin interaction that is required by a specific distribution of electrons over every dots; (b) To find out the temperature effect on the electron distribution in the dots; (c) To calculate the spin transport and the electron distribution in the dots in the presence of various magnetic field. Semiconductor
nanocrystals
Contact: Dr Chen Tupei Description: Starting from experimental results, the objective is to model and predict structural, physical and electronic properties and reliability of gate dielectric atomic layers/Si systems for nanoscale MOS devices. The rapid advancement in ULSI technology has pushed the feature size of MOS devices down to the sub-100nm range, and accordingly the gate oxide is reduced to sub-2nm. As the gate oxide thickness is reduced to just several atomic layers, it is expected that the structural, physical and electronic properties of the sub-2nm oxide/Si system will be different from that of thicker oxide/Si system. Actually, our recent experimental results strongly support this argument. For example, from the TEM experiment we observed a dependence of the lattice spacing in Si surface region on the oxide thickness. We believe the following computations will be important and useful for both fundamental research and device applications: dependence of Si surface (or interface) structure and surface strain on the thickness of the atomic layers, electronic structures including energy band offsets (barrier heights) and state density function at the atomic layers/Si interfaces, optical constants and dielectrics functions of the atomic layers, energy band structure of the atomic layers and its influence on the direct tunneling, etc. We understand that these computations are not easy, however, they can help us very much to understand the experimental results. Reliability of the gate dielectric atomic layers is a major concern in nanoscale MOS devices. Monte Carlo simulation can be used to investigate both the degradation of the gate dielectric including defect generation (charge trapping and neutral traps) in the gate dielectric and at the interface and the breakdown. Recently, we have conducted a Monte Carlo simulation on gate oxide breakdown based on a percolation model. We would like to extend the simulation to a more complicated scenario that covers from a single percolation path (first soft breakdown) to multiple paths (hard breakdown). One of our hopes is to extract the quantitative information of defect generation at various stressing fields and at different temperatures by comparing the simulation with the experiments. Semiconductor
band structure calculations
Contact: Dr Fan Weijun Description: We will investigate the band structures of InGaAsN/GaAs quantum wells (QWs) and quantum dots (QDs) using 6-band and 8-band effective mass theory. The strain effect and many-body effect will be included. And, the energy dispersion curves, density of state, optical gains and threshold current densities of the QWs and QDs will be obtained. Device
modeling of breakdown in ultrathin gate dielectrics in nanoscale CMOS
Contact: Dr Pey Kin Leong Description: The industry’s demand for greater integrated circuit functionality and performance at lower cost requires an increased circuit density, which has translated into a higher density of transistors on one wafer. This rapid shrinking of the transistor feature size has forced the channel length and gate dielectric thickness to also decrease rapidly. However, scaling limit issues including band offset, high gate leakage, boron penetration, channel mobility and oxide breakdown restrict the further shrinking of the device dimension. Beyond these scaling limits, research of dielectric integrity for gate oxides in the 4nm range and below will be required. Therefore, to study the breakdown mechanism of ultra-thin gate dielectrics in MOSFET and the device behavior after breakdown is very important and challenging. So far, there are many different models developed by researchers, i.e. Percolation model, Percolation Path Resistance model, Percolation Path Dilation model and so on. However, as the device continues downscaling, more and more reliability issues will be emerging and many of the existing physical models proposed by people might be lose validity. Thus, we should continue furthering our study and utilize our intelligence to develop more reasonable, accurate modes to suit the dielectric failure mechanism of non-stopping-down-scaling devices, to better understand the dielectric breakdown mechanism and eventually develop higher-quality dielectric continues to be a major challenge as the device continues to be scaled down into nano metrics. STM/BEEM is a microscopical technique that allows the investigation of electrically conducting surfaces down to the atomic scale. The reason for the extreme magnification capabilities of the STM/BEEM down to the atomic scale is mainly the physical properties of the tunneling current. The tunneling current flows across the small gap that separates the tip from the sample, a case that is forbidden in classical physics but that can be explained by the better approach of quantum mechanics. The current flow is very sensitive to the distance between the tip and surface, through this way, real space atomic resolution images of a sample surface are now possible. In this project, we plan to perform modeling on breakdown for gate dielectric including conventional gate silicon oxide and high-k with poly-Si and metal-gate. The results will be studied with the surface information acquired from STM/BEEM research. SiC
device design, simulation, fabrication and characterization
Contact: Dr Rusli Description: Most traditional integrated circuit technologies based on silicon (Si) devices are not able to operate at temperatures above 250C. Crystalline silicon carbide (SiC), aluminium nitride (AlN), gallium nitride (GaN), boron nitride (BN), diamond and zinc selenium (ZnSe) are some of the semiconductors with wide energy bandgap that are suitable for higher temperature operation (> 350C). Among these semiconductors, SiC has emerged as the most promising due to several advantages it possesses, which include availability of commercial substrates, known device processing techniques, the ability to grow thermal oxide for use as masks in processing, device passivation layers and gate dielectrics. Indeed, SiC is the only compound semiconductor that can be thermally oxidized to form a high quality native oxide. Thus, it is possible to make all the devices found in Si integrated circuit technology using SiC. Despite the rapid advances in material and device technologies ever since the first introduction of SiC single crystal wafer around 1990, SiC is still immature as a semiconductor material. There are a number of critical material and processing issues that are still under active investigation. Our research work aims to fully develop the process capabilities for fabricating high temperature, high power and high frequency SiC electronic devices. We propose to investigate, develop and optimize various SiC device fabrication processes, such as metallization, formation of ohmic and Schottky contacts, ion implantation, etching and surface passivation. With the developed processes, we will proceed to fabricate and characterize SiC Schottky diode and MESFET devices. Simulation of the device performance is carried out in parallel with the device fabrication and characterization. It will help us to better understand the performance of the SiC Schottky diode and MESFET devices, and assist in the design and optimization of the devices. Nanosolid
and nanometrics: Functional materials design and characterization
Contact: Dr Sun Chang Qing Description: Based on the original premises of surface bond contraction and sp-orbital hybridization of C, N and O (interacting with solid surface with production of nonbonding lone pair, hydrogen-like bond and anti-bonding dipoles), a "bond order-length-strength" (Bond-OLS) correlation mechanism has been developed for surface and nanosolid. Driven by the above initiatives, encouraging progress has been made recently in practical applications such as photonic crystals with tunable band gaps and intense photoluminescence of PZT as well. The objective of this initiative is to refine the Bond-OLS correlation mechanism for design and data interpretation of nanosolid or its assemblies for controllable growth of nanosolid with designed properties in mechanics, thermal dynamics, acoustics, optics, dielectrics, magnetization, for device application purpose. The long-term goal is to develop: (i) a general, yet simple, model covering as far as the possible changes due to shape and size effect, for designing the nanomaterials and to provide guidelines for nanosolid growth; (ii) technique deriving information about the behaviour of a single atomic bond and the single energy level of an isolated atom as well as the crystal binding intensity; and eventually, (iii) minimizing the gap between atomic scale and micrometric scale.
We also study the optical properties of quantum wells semiconductor materials including the AlGaAs/GaAs, InGaAs/InP, InGaAs/GaAs and InGaNAs/GaAs quantum wells. Optical parameters such as absorption coefficient, gain and refractive index as well as the influence of intermixing effects can be investigated from our computer models. We are now working on wide bandgap materials study such as Zinc Oxide thin films and its potential to fabricate high power UV semiconductor lasers. We had collaboration with researchers in The University of Hong Kong, Department of Electrical & Electronics Engineering. We have also developed computer simulators for optoelectronic industries such as Agere Systems in USA to analyze 0.98µm high power semiconductor lasers. We have successful secured funding from the Hong Kong government for more than HK$3.5 millions as well as obtained funding from NTU (AcRF) and A*STAR (Singapore government) for more than S$2 millions. Our research leader, Siu-Fung YU has also been invited to serve as one of the guest editors of the IEEE Journal of Selected Topics in Quantum Electronics in the area of 'Optoelectronics Device Simulation' for the May/June 2003 issue. We are a small research group but with significant impact to our optoelectronic society.
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 Research
Collaboration
The Computational Nano-Electronics Group or its members have on-going collaborations with the following institutions/organizations: Singapore
Institute of Manufacturing Technology (SIMT)
and Institute of High Performance Computing (IHPC)
SIMT Staff: Dr Collier Peter Anthony IHPC Staff: Dr Li Er Ping, Dr Wu Ping, Dr Yang Shou Wang, Dr Bai Ping NUS Staff: Dr Loh Kian Peng, Dr Chin Wee Shong UIUC Staff: Prof Umberto Ravaioli Purdue Staff: Prof Supriyo Datta NTU Staff: Dr Zhou Xing
NTU Staff: Dr Ang Lay Kee, Richy LANL Staff: Dr Thomas J. T. Kwan UMich Staff: Prof Y. Y. Lau
NTU Staff: Dr Rusli Auburn Staff: A/Prof Chin-Che Tin
Institute
of Microelectronics (IME)
IME Staff: Dr Rustagi Subhash (PI), Dr Xiong Yongzhong, Dr Shi Jinglin, Dr Guo Lihui, Mr N. Ranganathan, Mr Navab Singh NTU Staff: Dr Zhou Xing NUS Staff:Dr Koen Mouthaan
NTU Staff: Dr Zhou Xing IME Staff: Dr Lakshmi K. Bera, Dr Balasubramanian Narayanan, Dr Rustagi Subhash
NTU Staff: Dr Zhou Xing CSM Staff: Dr Lap Chan, Dr Sanford Chu, Dr Khee Yong Lim LSIL Staff: Dr Peter Bendix NTU Staff: Dr Zhou Xing, Mr Chiah Siau Ban, Mr See Guan Huei CSM Staff: Dr Liang Choo Hsia, Dr Sanford Chu, Dr Michael Cheng, Dr Chew Hoe Ang SRC Staff: Dr James Hutchby
IITB Staff: Prof Mahesh Patil NTU Staff: Dr Zhou Xing
RCNS Staff: Prof Mitiko Mirua-Mattausch NTU Staff: Dr Zhou Xing |
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Research
Funding
A*STAR (2005-2008, Dr Ang Lay Kee, Ricky)
NTU - ARC (2004-2007, Dr Chen Tupei)
A*STAR (2005-2008, Dr Fan Weijun
A*STAR (2004-2007, Dr Pey Kin Leong)
NTU - SUG (2002-2005, Dr Yu Siu Fung)
A*STAR (2002-2005, Dr Yu Siu Fung)
NTU - RGM (2002-2005, Dr Yu Siu Fung)
SRC® (2004-2005, Dr Zhou Xing)
NTU-RGM (2004-2007, Dr Zhou Xing)
A*STAR (2004-2007, Dr Zhou Xing)
NTU - SUG (2002-2003, Dr Ang Lay Kee, Ricky)
NTU - AcRF (2001-2004, Dr Chen Tupei)
A*STAR (2001-2004, Dr Rusli)
NTU (2002-2003, Dr Sun Chang Qing)
DSO (2000-2003, Dr Yu Siu Fung) |
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Research
Facilities
Analog Artist Design Environment, Analog Artist Statistical Analysis, Virtuoso Interface CCT IC Craftsman, Clock Tree Generator for Silicon Ensemble, Composer, Diva/iLVS/iDRC/iLPE, Dracula III Advanced Bundle (DRC/ERC/LVS/LPE) IC, HSPICE Interface, IC Craftman - Virtuoso I/F, Journeyman CCT IC Craftman, Leapfrog VHDL Simulator IC, Mixed-Signal Back Annotation Interface, Pearl Full Custom IC, Physical Design Planner HLDS, Silicon Ensemble DSM IC, Spectre Advanced Circuit Simulator / RF Option, Stream to/from Cadence, Substrate Coupling Analysis, Verilog-XL, VHDL Model Import Option for Verilog-XL, Virtuoso Layout Editor
Accusim II, Autologic Block, Autologic HDL-VHDL, Autologic Optimizer, Autotherm, Board Stn, Design Architect, Falcon Framework, Hybrid Stn, IC Layout Ex Stn, Quickfault II, QuickGrade II, Quickpath, QuickSim II, QuickHDL-VHDL, QuickHDL-Pro, WorkXpert
RFIC/RF Board Design Stations - Design Environment, Linear/NonLinear Simulators, Circuit Envelope Simulator, Statistical Design, RF Passive Circuits/System Models, RF Passive SMTTransistor Library, Multilayer Interconnect Models, Momentum EM Simulator Engine, Layout, High Frequency SPICE, Convolution Simulator, Spice Model Generator, GDSII Translator, Spice Netlist Translator, High Frequency Structure Simulator, HFSS Optimization Add-on NLS, HPtolemy Fixed point Analysis, HPtolemy Simulator, HPtolemy Matrix Model, Digital Filter ADS, IC-CAP (Agilent)
Behavioral Compiler, COSSAP, Cyclone, DC-Expert, DesignAnalyzer, DesignCompiler, DesignTime, DesignWare, ECO-Compiler, FPGA-Compiler, FPGA-Library-Compiler, Floorplan Manager, HDL-Compiler, Library-Compiler, MCE-Lib, Power-Optimization, PrimeTime, Protocol-Compiler, RTL-Analyzer, Test-Compiler, Test-Library, TestManager, TestSim, VHDL-Compiler, VSS StarHspice, StarSim, Libra-Passport 0.35 micron & 0.6 micron Library Full suite of Synopsys (Avant!/TMA) TCAD tools running on >20 networked Ultra Sparc workstations
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