Unified Approach to MOS Transistor Compact Modeling

Xing Zhou, Ph.D.

School of Electrical & Electronic Engineering,

Nanyang Technological University, Singapore 639798

(exzhou@ntu.edu.sg)

Figure 1. Seamless transformation and unification of MOSFETs: (a) partially-depleted (PD) silicon-on-insulator (SOI), (b) fully-depleted (FD) ultra-thin body (UTB) SOI, (c) asymmetric double-gate (a-DG), (d) symmetric double-gate (s-DG), (e) “bulk-UTB”, and (f) bulk.

Keywords: Compact model (CM), charge-sheet model (CSM), inversion-charge model (ICM), surface-potential model (SPM), threshold-voltage model (TVM), unified regional model (URM), MOSFET.

Abstract

MOSFETs have been the building blocks of modern VLSI for decades. As classical bulk-CMOS scaling is approaching its physical limit, various types of non-classical CMOS emerge. Although different in structure, topology, and operation, different types of MOS transistors essentially function in a similar way governed by the same physical principles, and they are related one another as illustrated in Fig. 1. Accompanied with technology advancement, MOS compact models (CM) that are used in circuit simulators for designing integrated circuits have gone through many generations of development. Learning from past experience, it is important to construct a core model that is extendable to future technologies and devices rather than always “chasing” the technology. A careful examination of the fundamental physical equations governing various types of devices and operations is therefore necessary in order to come up with an approach to unifying various models into one framework.

In this paper, we review the basic voltage equations for the generic MOS transistor. We extend our unified regional modeling (URM) approach to bulk-MOS charge modeling with non-pinned surface potential for various device structures, such as partially-depleted (PD) or fully-depleted (FD) ultra-thin body (UTB) silicon-on-insulator (SOI) as well as symmetric/asymmetric double-gate (s‑DG/a‑DG) MOSFETs. The regional solutions make it easy to handle different device structures with explicit asymptotically physical solutions, and the unified solution combines the best features in different modeling approaches, such as surface-potential/inversion-charge/threshold-voltage based models, without the need to solve exactly at flat-band voltage. We show that it is viable to obtain a unified solution scalable with layer thickness and doping in all bias ranges (accumulation, depletion, weak/volume/strong inversions). In particular, the effect of doping (even unintentional) in DG MOSFETs is studied with the regional approach. The ultimate goal is to have one generic and scalable model with selectable accuracy and seamless transition across device types and operations.

Introduction

The most complete MOSFET model for the implicit (input) voltage equation [1] and double-integral (output) current [2], and the simplest drift-current model [3] based on fixed bulk-charge and pinned surface-potential were both proposed by Sah 40+ years ago; the former still serves as the “golden reference” for benchmarking bulk-MOS compact models and the latter is taught in all elementary MOSFET theory. For an “ideal” long-channel uniformly-doped MOSFET, either model can be used for describing terminal characteristics (the simple model is preferred for device/circuit analyses); whereas for a nanoscale MOSFET, neither model is sufficient to be used without taking into account various short-channel/narrow-width/high-field/quantum effects. The history of MOS transistor CM development [4], since the introduction of the charge-sheet model (CSM) [5], has followed the “simple” threshold-voltage (V_t) modeling (TVM) formalism for three decades, not because of people not being aware of the “complete” physical description by the surface potential (f_s) but mainly due to not having such high accuracy demand offered by the surface-potential models (SPM) in the early days for digital designs. Inversion-charge (Q_i) modeling (ICM) approaches seek to overcome some major obstacles in V_t-based models (such as symmetry and continuity) through a linearization of Q_i with respect to f_s; whereas f_s-based formulations describe the terminal charges/currents in terms of f_s, which is solved iteratively or explicitly from the (input) voltage equation.

High accuracy demands drive the development of more accurate description of surface potentials and charges [6]. Although it is known that accurate iterative f_s solutions for bulk-MOS are readily available, the question is: will the iterative (whether by numerical or analytical) f_s-based formalism be the best core model for future generations of various types of MOS devices?

As bulk-CMOS scaling is driven to its limit, various non-classical devices emerge, such as ultra-thin body (UTB) and silicon-on-insulator (SOI) MOSFETs. For SOI MOSFETs, the fundamental input voltage equation will be modified due to the change in the bottom boundary condition. Depending on the channel thickness and doping, the SOI MOSFET may work in partially-depleted (PD) or fully-depleted (FD) mode. Another scalable parameter would be the bottom oxide thickness which, if comparable to the gate oxide thickness, results in asymmetric double-gate (a‑DG) operation; or a symmetric-DG (s‑DG) device when the top and bottom oxides and the front- and back-gate biases become the same, such as in a FinFET. Although these different types or operations of devices have distinct technologies and topologies as well as applications, transitions from one type to another should really be seamless (from a theoretical point of view) when physical layer thickness as well as doping and bias are varied. Now, the question is: do we want different core models for different types of devices, or one unified model that can handle all device types and operations? The real question (or challenge) is the right choice of model infrastructure that is extendable and flexible such that, when non-classical alternative devices emerge in real applications, the model under development will be ready with seamless transitions from “bulk-like” to “DG-like” structures. Figure 2 illustrates the history and future trend of MOS transistor compact models.

Figure 2. Classical and non-classical MOSFET compact models: history and future.

It can be very challenging (if not impossible) to handle all these device types within the same iterative/explicit f_s-based core model, since it is known the solution to the voltage equation is non-integrable for doped s‑DG/a‑DG devices. This may be the reason why existing literature on DG models all assumes undoped channel. However, a model developed with “undoped” assumption cannot be extended to doped devices; nor can it accurately model real devices in which unintentional doping is always present. On the contrary, a model developed with doping scalability, although much more difficult, contains undoped devices. The motivation in extending our URM approach to surface-potential and charge modeling for bulk-CMOS [7] to SOI/DG MOSFET modeling is an attempt to unify various types of devices with different governing equations.

Unification of MOS Models

The Master (Input) Voltage Equation

Using nMOS as the example and following the coordinate in the generic MOSFET structure shown in Fig. 3, and under the gradual-channel approximation (GCA): d²y/dy² << d²y/dx², the Poisson equation is written as

Figure 3. Generic MOSFET structure and schematic potential distributions for three cases.

(1)

Based on E_x = ‑dy/dx, using the following transformation

and the “generic” boundary conditions (at x = 0 and x = x₀)

(2a)

, (2b)

(1) can be integrated out as

(3)

The general boundary conditions are given for SOI/DG using the Gauss law at the front/top gate (x = 0):

(4a)

and the back/bottom gate (x = x₀ = t_Si; E₀ = E_b, f₀ = f_b):

(4b)

where V_g and V_b are the front- and back-gate voltages, V_FBj = f_MSj ‑ Q_oxj/C_oxj and C_oxj = e_oxj/t_oxj are the flat-band voltage and oxide capacitance (per unit area), with e_oxj and t_oxj being the oxide permittivity and thickness, respectively, for the front and back gate (j = f, b). Applying (4) to (3), one obtains one generic master (input) voltage equation with two unknowns (f_s and f_b), which can only be solved (conceptually) after assuming another relationship between them, since the second double-integral equation cannot be solved if doping is considered, which is given by the most generic expression below:

(5a)

(5b)

(5c)

(5)

This is the most generic case for a‑DG MOSFETs, which is also the most difficult one to solve when doping is considered. When doping is not considered, (5) is integrable, which gives the second equation relating f_s and f_b.

The (Input) Voltage Equation with f₀^' = 0

Asymmetry in DG arises whenever the two gate’s V_FBj, t_oxj, e_oxj (j = f, b), as well as V_g and V_b are different. For symmetric DG with identical gate materials, oxide thickness, and V_g = V_b, the potential gradient at the mid-gap (x₀ = t_Si/2) is always zero (E₀ = ‑f'₀ = 0). This is also similar to the bulk-UTB with f'₀ = 0 at x₀ = t_Si, which is equivalent to one half of the s‑DG. For FD-SOI when the bottom oxide thickness t_oxb ® ¥, from the boundary condition (4b), E_b = ‑f'_b » 0. Under these conditions, (3) can be simplified to the following normalized surface field:

(6)

in which j_s = f_s/v_th, j₀ = f₀/v_th, and v_c = V_c/v_th are the normalized (to the thermal voltage, v_th) surface potential, potential at x = x₀, and channel voltage, respectively. Applying the boundary condition (4a) to (6), it gives one (input) voltage equation for the (front) gate:

(7)

for the (coupled) f_s and f₀ solutions, in which g = (2qe_SiN_A)^1/2/C_ox is the body factor, and

(7a)

However, the second boundary condition (4b) cannot be written at x = x₀ since there is no Gauss law to be applied at that “boundary.” Again, another relationship between f_s and f₀ has to be found or assumed in order to solve the voltage equation (7) with f'₀ = 0 for s‑DG/bulk-UTB MOSFETs. It is also clear to see that (7) is not integrable if doping (N_A term) is considered. However, regional solutions can be derived for the doped s‑DG MOSFETs [8].

The Bulk-MOS (Input) Voltage Equation

It can be observed that when f₀ = 0 in (7), which is equivalent to bulk-MOS (and approximately PD-SOI) boundary condition, it reduces to the conventional bulk-MOS “Pao–Sah” voltage equation [1, 2, 4]:

(8)

It is noted that (8) has used the correct remote minority carrier boundary condition [4] in the N_D » n_¥ term in (1), which has no negative f_f as V_gb approaches V_FB. (8) can be solved exactly by numerical iteration, or explicitly by analytical approximations, as is widely used in f_s-based bulk-MOS models.

Unified Surface-potential and Charge Solutions

CSM and f_s Solution Near Flat-band

All contemporary bulk-MOS compact models employ the CSM [5] to overcome the mathematical difficulty in the second integration of the Poisson equation, or the (input) voltage equation (8), which basically equates the total gate (plus fixed oxide) charge to the induced charge in the channel/substrate (Q_sc) through charge neutrality:

(9)

or, defining normalized (by C_ox) “charges,” q_x º Q_x/C_ox, (9) is equivalent to (8):

. (9a)

The left-hand side (LHS) of (9) is described by f_s, whereas the right-hand side (RHS) is non-integrable if doping (N_A) and either holes (p in accumulation) or electrons (n in inversion) are both present. The CSM attempts to separate the (mobile) inversion charge (Q_i) from the (fixed) depletion charge (Q_b): Q_sc = Q_i + Q_b, and by assuming a sheet of charge for Q_i and using depletion approximation for Q_b, terminal charges and currents can be integrated out across the channel of a MOSFET. However, in f_s-based models, accurate solution of f_s is essential, and none of the terms in (8) can be ignored near the flat-band voltage.

Iterative/Explicit f_s Approach

The iterative approach (for bulk MOS) attempts to solve the full voltage equation (8) exactly through numerical methods; or by “iterating” a few times the approximated analytical equations from (8), or some mathematically “conditioned” form of (8). Either approach has been shown to give accurate and physical f_s solutions. However, beyond the bulk-MOS equation (8), it is nontrivial to be extended to devices whose governing equations are given by (7) [or (3)–(5)] when the surface potential is coupled with the back-gate or mid-gap potential.

Essence of the Unified Regional Approach

Regional solutions to (8) can be easily obtained when f_f is approximated regionally by

(10)

which has the following (piece-wise) solutions:

. (11)

The unified regional solutions

(12)

can be obtained [7] through two interpolation functions

(12a)

. (12b)

The key feature (or difference from iterative/explicit f_s solution) is that the solution at flat-band is not solved exactly in each regional piece, but the combined one (f_sa = f_acc + f_sub) gives physical solution at flat-band, which can be easily tuned through two parameters (s_a, s_f) to meet the smoothness and charge neutrality at flat-band [7, 9]. Although the accuracy would not be as good as the iterative solution, the URM captures the essential physics asymptotically while avoiding the complicated solution near V_FB.

However, the single-piece unified f_s,eff solution will not be used the same way as in f_s-based models; rather, unified regional charges are the essence of the approach. This has been demonstrated in the bulk-charge (Q_b) modeling [7], which is based on the identity V_gb ‑ V_FB º V_gba‑ V_gbr where V_gba is the “forward” interpolation function

(12c)

(x = V_gb ‑ V_FB) having the same parameter (s_a) as in V_gbr. This allows the LHS of (9) (gate charge) to be decomposed into the sum of accumulation and depletion charges:

(13)

where

(13a)

(13b)

in which another (approximate) “identity” has been used:

(13c)

due to the use of the same parameter (s_f) in V_gbf and f_sub. The Q_b,sub defined above, which relates to the RHS of (8) (channel induced charge), is almost identical to the LHS of (8) Q_b,sub1 = ‑C_ox(V_gba ‑ f_sub) in the above derivation for bulk charge, as shown numerically by the difference (< 10^‑11 % relative “error”), DQ_b,sub = |Q_b,sub ‑ Q_b,sub1|, in the inset of Fig. 4, which is always true for any device geometry and bias. With the complementary interpolation functions, the decomposed regional charges cross the flat-band smoothly (see Fig. 4), rather than “abruptly” as in f_s-based CSM, which requires highly accurate solution close to the flat-band voltage.

Figure 4. Unified regional bulk–gate capacitance (‑dQ_b/dV_g) and its components, compared with Medici data. The inset shows the absolute difference in the two depletion-charge expressions.

Extending to SOI/DG MOSFETs

When extending the bulk model to SOI/DG MOSFETs, the advantages of the unified regional approach become apparent, since it will not be as “easy” (as for bulk), if not impossible, to solve the new voltage equations for the coupled front/back-gate or mid-gap potentials with the iterative/explicit SPM approach. Also, CSM fails when “volume inversion” occurs in UTB/FD-SOI/DG devices. However, with the URM approach, solutions to (7) are possible, as will be shown for the results in the next section.

Results of Various Structures

In this section, we present our model results for various device structures compared with the same (ideal) numerical device from Medici, with an emphasis on the smooth/seamless transitions across device types and operations. Detailed formulations have been developed in [8] for doped s‑DG based on URM approach, in [10] for undoped s‑DG/a‑DG/SOI based on Newton–Raphson (N‑R) iterative method, and in [11] for undoped s‑DG/a‑DG/SOI based on explicit regional models. The most challenging task is to model the doped a‑DG MOSFETs, which is our ongoing effort.

Figure 5. Surface and mid-gap potentials for doped s‑DG and their regional components. The “turning” points at flat-band (V_FB), full-depletion (V_FD), and threshold voltages (V_t) are all physically derived with doping and layer thickness scalability.

Doped s-DG/UTB/SOI MOSFETs

For s‑DG (including bulk-UTB and FD-SOI with large t_oxb) MOSFETs in which f'₀ = 0 can be assumed, (7) is the governing equation, which is similar to the bulk-MOS voltage equation (8), if a relationship between f_s and f₀ can be found [8]. Figure 5 shows the regional solutions (in accumulation, depletion, weak/volume inversion, and strong inversion) of the surface and mid-gap potentials for a doped s‑DG, as well as the unified solutions. Doping dependence in s‑DG/UTB MOSFETs (above flat-band) is shown in Fig. 6 for the URM validated with Medici data, which demonstrates the importance of including doping (even unintentional) in DG structures, since the error (in mV range) in f_s due to Fermi-level shift can be non-negligible if the model does not include the N_A term [8]. Channel thickness scaling is shown in Fig. 7 for the URM, in which total gate charge variation due to volume inversion is physically modeled. The model also converges to bulk as channel thickness increases.

Figure 6. Surface and mid-gap potentials for doped s‑DG for varying channel doping, showing convergence to undoped device.

Figure 7. Surface potential and gate charge for doped s‑DG/UTB at varying channel thickness, showing convergence to bulk device.

Figure 8. Explicit front/back-gate surface potentials for undoped a‑DG and their regional components, compared with the implicit solutions. The inset shows the absolute errors of the explicit solutions.

Undoped s-DG/a-DG/SOI MOSFETs

For undoped DG/SOI MOSFETs, since the Poisson equation can be integrated twice [12], a generic solution with Newton–Raphson (N‑R) iteration (with a very good initial guess) has been developed [10]. A URM approach has also been applied to undoped generic s‑DG/a‑DG/SOI devices [11]. Figure 8 shows the results of explicit regional front/back-gate surface-potential solutions for undoped a‑DG, with the absolute errors shown in the inset. Transition from a‑DG to s‑DG is shown in Fig. 9 with the URM when both gates are tied together (so, asymmetry arises from varying back-gate oxide thickness). In Fig. 10 and Fig. 11, a‑DG behaviors are well predicted by both the implicit and explicit solutions for t_Si and t_oxb variations, respectively, and verified in comparison with Medici data. Figure 12 shows the explicit surface potentials for two values of V_c, with < 6 mV error with respect to Medici, which are readily applicable in terminal-current evaluations at the source (V_c = V_s) and drain (V_c = V_d) sides.

Figure 9. Explicit front/back-gate surface potentials for undoped DG for varying back-gate oxide thickness, showing transition from a‑DG to s‑DG, compared with Medici data.

Figure 10. Front/back-gate surface potentials for undoped a‑DG from implicit and explicit (regional) solutions for varying channel thickness, compared with Medici data.

Figure 11. Front/back-gate surface potentials for undoped a‑DG from implicit and explicit (regional) solutions for varying back-gate oxide thickness, compared with Medici data.

Figure 12. Explicit and implicit surface potentials with channel-voltage variations, readily applicable in terminal-current evaluations, compared with Medici data. The inset shows the absolute error with respect to Medici solutions.

Doped a-DG/SOI MOSFETs

Doped a‑DG (including FD-UTB SOI) MOSFETs represent the most challenging to model due to non-integrable (5) and highly sensitive coupling between the front- and back-gate surface potentials. With the URM approach, accumulation, depletion, and weak/volume inversion regions can be solved since the regional voltage equations are integrable. However, when the front gate is in strong inversion while sweeping the front-gate voltage at fixed back-gate bias, accurate f_s solution is essential for solving f_b, which is non-integrable. This remains the final challenge in our URM solutions for the generic MOSFET. However, once overcome, the approach and solutions would be generic and applicable for s‑DG as well as undoped structures discussed previously. Our preliminary results for doped a‑DG are shown in Figs. 13–16, in which back-gate oxide thickness dependence (from a‑DG to FD-SOI) is shown in Fig. 13, channel-thickness dependence (from UTB to ‘bulk’) in Fig. 14, channel-doping dependence (from high doping to undoped) in Fig. 15, and back-gate bias dependence in Fig. 16, all physically scalable.

Figure 13. Explicit front/back-gate surface potentials for doped a‑DG/SOI, showing physical scaling with back-gate oxide thickness, compared with Medici data.

Figure 14. Explicit front/back-gate surface potentials for doped a‑DG, showing physical scaling with channel thickness, compared with Medici data.

Figure 15. Explicit front/back-gate surface potentials for doped a‑DG, showing physical scaling with channel doping (including undoped case), compared with Medici data.

Figure 16. Explicit front/back-gate surface potentials for doped a‑DG, showing physical scaling with back-gate bias, compared with Medici data.

Summary and Conclusions

Physical scalability and seamless transition over bias ranges (which is essential) and over geometry (which is critical) are fundamental requirements of a core model for circuit simulation. Model extension to various types of devices, such as existing bulk and SOI as well as emerging double-gate MOSFETs, may be only considered as a nice feature to have. However, seamless transition across device types and operations is a measure of the physics built in since transitions in real devices should really be seamless. The best of Einstein’s theory is not only a brand new theory, but one that includes old (Newton’s) theory as a special case. What have been proposed and demonstrated in this paper represents our efforts in building such a core model infrastructure in bridging today’s modeling requirements with future generation modeling demands for non-classical devices as the building blocks to design integrated circuits. Although such a “dream” model is very challenging, it pays to have a forward-looking model as well as a dynamic approach. Finally, we quote Albert Einstein: “Politics is for the present, but an equation is something for eternity.”

Acknowledgement

This work was supported in part by the Semiconductor Research Corporation (SRC) under Contract No. 2004-VJ-1166 through Research Customization Program supported by Chartered Semiconductor Manufacturing (CSM), in part by the Nanyang Technological University (NTU) under Grant RGM30/03, and in part by the Institute of Microelectronics (IME) under Agreement for Research Collaboration HN/OCL/103/0105/IME through the A*STAR SERC Grant No. 042 114 0045. The research team members include Siau Ben Chiah, Karthik Chandrasekaran, Guan Huei See, Raymond Selomulya, Guan Hui Lim, Wangzuo Shangguan, Zhaomin Zhu, Shihuan Lin, Chengqing Wei from NTU; as well as Subhash Rustagi from IME and Shesh Mani Pandey, Michael Cheng, Sanford Chu, Liang-Choo Hsia from CSM.

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