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Voltage-Controlled Oscillator (VCO)

The unity frequency ft, which is defined as the frequency where the transistor current gain becomes unity for 0.18µm is about 40 GHz for optimum biasing. In a circuit with large biasing swing like a VCO, the ft can be as low as 15 GHz. This proves to be a major problem for VCO design as the VCO needs to work at 24 GHz. In addition, other parameters like tuning range and phase noise could be greatly affected by the low unity frequency. The division has developed a VCO with an oscillation frequency of 23 GHz using CMOS transistor with ft of 15.8 GHz. Based on the 0.18µm CMOS process, it has been demonstrated that using novel push-pull buffer, a VCO can operate up to almost double the unity frequency.

IC Reliability

IC Reliability is another important aspect of IC design, especially with the continuous reduction in line width and the increasing in the number of metallization layers. Our colleagues have developed the physical modelling of the electromigration that allows accurate prediction the failure sites for interconnects with different line widths and structures under various stress conditions. With the model, different category of failure mechanisms could be predicted for failure analysis.

Digital Signal Processing

High-speed Digital Signal Processing (DSP) is a dedicated module that has to cope with the complexity and diverse processing requirements and specifications of different SoC systems. Traditional techniques for multiplierless filtering are to optimize the digital filter coefficients in signed power-of-two (SPT) coefficient space, and thus the coefficient multiplications are replaced by additions and shifts. However, the design of digital filters with discrete coefficient values may not always be possible in some applications such as in adaptive filtering. The division has developed a new technique where signals are converted into a sum of a limited number of SPT terms. Since hardware circuitry for the real time conversion is available, the filter is also multiplierless even though the coefficient values are not SPT. The new technique could handle very complex signal processing needs with low power consumption.

With high-speed electronic systems operate at sub-nano second edge rates, board-level integration becomes a very challenging task. The interconnects begin to behave as transmission lines. In addition, parasitic effects due to inter-layer vias, interconnect bends and gap in ground plane, start to show their impacts on circuit performance at these edge rates. Hence, Signal Integrity (SI) and EMC are becoming major issues for high-speed board design. The SI and EMC issues, if not properly resolved, will lead to unstable and intermittent operation problems. The research group in EMERL has done extensive research work and have developed a systematic design methodology in SI/ EMC compliant high-speed designs.